1. Field of the Invention
The present invention relates generally to processes for fabricating integrated circuits and semiconductor devices, and more particularly to a method of forming MOS devices having steep diffusion region profiles.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Ion strikes on drain nodes of semiconductor memory devices, such as static random access memory (SRAM) devices for example, can perturb drain node voltages and can flip the state of the device resulting in a single event upset (SEU). In particular, ion strikes can generate electron-hole pairs which travel along the path of a single energetic particle as it passes through the depletion region of memory cells where reverse biasing is applied between a drain region and well of a transistor. Sources of these ion strikes include alpha particles from radioactive materials and particles generated by neutrons from cosmic rays. Due to the rearrangement of charge carriers following an ion strike, a depletion region can collapse and, in turn, funneling from the depletion region can result from minority carrier flow through the substrate. As a consequence, the drain node voltage is perturbed and the state of the memory device may be flipped. The length of the funneling and the time period or duration thereof are dependent on well doping concentration. In some cases, feedback enables or causes the memory device to be flipped continuously until an input is applied to the device. After the depletion region recovers from the ion strikes, holes formed in the well region during funneling are pushed out by an electric field produced by normal biasing and the pre-ion strike potential is restored.
To reduce the occurrence of SEUs, which is commonly referred to as the soft error rate (SER), it is desirable for: (i) the voltage perturbation on drain nodes be as small and short as possible; (ii) recovery be as fast as possible; and (iii) feedback be as slow as possible. Generally, there are three avenues with which to approach resolving or preventing the problems associated with ion strikes. These include intervention at the process technology level, circuit level, and the system level. Typically, circuit and system level approaches reduce performance of memory devices and/or result in a severe area penalty through the addition of devices, such as body taps to the circuits. Several known process level approaches rely on the fact that having higher well doping concentrations improves SER by providing shorter funneling length, higher well conductance, and faster recovery. In addition, higher well conductance may also reduce single event latch-up (SEL) occurrences, which is another type of failure in CMOS technologies. SEL occurs when neighboring NMOS and PMOS regions form parasitic bipolar junction transistor circuits which result in destructive device failure due to excessive substrate current. It is believed that SEL failures can be reduced by decreasing the input node bias values in parasitic bipolar junction transistor circuits. For example, higher well concentrations may be used to in turn produce higher well conductance to decrease the input node bias values.
There are a few approaches that may be used to achieve high doping concentrations in well regions. One utilizes a retrograde well implant before gate definition. Although a retrograde well implant may provide an improvement over previous devices having standard doping in well regions, the level and gradient of impurity concentration within the well (referred to herein as the steepness of the well) is limited by both the design specifications of the ensuing transistor and the fabrication steps used to form the transistor. For instance, an implant dose used to produce a well may be limited by channel region design specifications. In particular, too high of an implant dose for a well region can undesirably affect the doping concentration of a channel region formed for an ensuing gate structure. In addition, the well implants may diffuse during subsequent thermal processing steps used to form the gate structure and, therefore, the concentration and gradient level of impurities within the well may change, and most likely move to leveling out from their implanted state.
Another approach utilizes additional implants after the formation of tip or source/drain regions on opposing sides of a patterned gate structure. The higher well concentration produced by this approach, however, results in higher capacitance at the junction between the source/drain regions and the well region and, consequently, a lower junction breakdown voltage level. Moreover, steepness of the well is limited to the impurity profile as implanted. Another known approach for producing high well doping concentrations includes the use of epitaxial (EPI) wafers or substrates in which retrograde wells are prefabricated. This approach is also not wholly satisfactory for a number of reasons. First, the cost of EPI substrates is substantially more expensive than standard substrates or wafers. Second, EPI substrates are generally formed of one conductivity type. Hence, the benefit of using an EPI substrate to achieve high well concentration is limited only to one type of device, either NMOS or PMOS. Third, in order to effectively reduce the overall SER a very thin EPI layer has to be grown on top of the substrate, causing process control and variability issues. Thus, using EPI substrates is not optimal reducing SER within memory devices.
Accordingly, it would be advantageous to develop a method for producing MOS devices having well regions with steep well profiles, whereby the SER resulting from such devices is improved. It is further desirable that the method improve SEL and MOS performance while minimizing junction capacitance degradation. It is still further desirable that the method also improve short channel effects and contact resistance of the MOS device produced thereby.